Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs

Hsien-Ho CHUANG; Jing-Yang JOU; C. Bernard SHUNG

Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs

Hsien-Ho CHUANG, Jing-Yang JOU, C. Bernard SHUNG

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A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired non-homogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of non-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates favorable results for Xilinx XC4000 CLBs. Over a set of MCNC benchmarks, our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2545-2551

Publication Date: 2000/12/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Performance Optimization

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Hsien-Ho CHUANG, Jing-Yang JOU, C. Bernard SHUNG, "Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs" in IEICE TRANSACTIONS on Fundamentals, vol. E83-A, no. 12, pp. 2545-2551, December 2000, doi: .
Abstract: A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired non-homogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of non-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates favorable results for Xilinx XC4000 CLBs. Over a set of MCNC benchmarks, our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2545/_p

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@ARTICLE{e83-a_12_2545,
author={Hsien-Ho CHUANG, Jing-Yang JOU, C. Bernard SHUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs},
year={2000},
volume={E83-A},
number={12},
pages={2545-2551},
abstract={A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired non-homogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of non-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates favorable results for Xilinx XC4000 CLBs. Over a set of MCNC benchmarks, our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2545
EP - 2551
AU - Hsien-Ho CHUANG
AU - Jing-Yang JOU
AU - C. Bernard SHUNG
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired non-homogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of non-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates favorable results for Xilinx XC4000 CLBs. Over a set of MCNC benchmarks, our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.
ER -