Recently, most signal processing algorithms have been developed with floating-point arithmetic, while the fixed-point arithmetic is more popular with most commercial devices and low-power real-time applications which are implemented on embedded/ASIC/FPGA systems. Therefore, the optimal Floating-point to Fixed-point Conversion (FFC) methodology is a promising solution. In this paper, we propose the FFC consisting of signal grouping technique and simulation-based word length optimization. In order to evaluate the performance of the proposed technique, simulations are carried out and hardware co-simulation on Field Programmable Gate Arrays (FPGAs) platform have been applied to complex Digital Signal Processing (DSP) algorithms: Linear Time Invariant (LTI) systems, multi-mode Fast Fourier Transform (FFT) circuit for IEEE 802.11 ax WLAN Devices and the calibration algorithm of gain and clock skew in Time-Interleaved ADC (TI-ADC) using Adaptive Noise Canceller (ANC). The results show that the proposed technique can reduce the hardware cost about 30% while being able to maintain its speed and reliability.