CMOS circuits consume great dynamic power in switching. It has been proposed that energy transfer through a rising Vdd dissipates small amounts of energy. In typical power gate circuits, the high-performance PMOS transistors (PSW) that connect the circuit blocks to the power supply reduce leakage power by shutting off outer power (Vdd) to the idle blocks. We expand this technique by utilizing active PSW, which are turned on and off by clock signal. The PSW are fully turned on only for half of each clock cycle. This means that sufficient Vdd is provided to the circuit continuously for half of each clock cycle. In this manner, the circuit charge and discharge actions are cycle occur in different phases, and ramp Vdd is supplied to the designed circuit; we name this technique "CKVdd." CKVdd is a clock-controlled self-stabilized voltage technique, which generates stable ramp voltage to suppress the currents effectively. It is proposed to reduce dynamic power dissipation in conventional CMOS digital circuits. As compared to the conventional circuit, the circuits using CKVdd technique possesses several characteristics that differ from those of the current circuits using constant Vdd power source. First, CKVdd technique combines the power source and clock signal; it is an efficient low power technique. Second, CKVdd propose a feasible method to generate ramp-Vdd and low-Vdd. This technique would be convenient used to design generic low power digital circuits. Third, normal CMOS circuits show the dynamic power consumption increase proportional to the clock frequency. CKVdd results in a lower-than-usual frequency dependency, it is suitable used to design high clock speed circuits. In investigating constant Vdd for MPEG VLD decoders, CKVdd-circuit reduces 48% of the usual power dissipation and 88% of the usual peak current with small delay penalty.

The purpose of a testability analysis program is to estimate the difficulty of testing a fault. A good measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Among those, the Controllability and Observability Procedure COP can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy in COP is due to the ignorance of signal correlations. Recently, the algorithm of TAIR in [5] proposes a testability analysis algorithm, which starts from the result of COP and then gradually improves the result by applying a set of rules. The set of rules in TAIR can capture some signal correlations and therefore the results of TAIR are more accurate than COP. In this paper, we first prove that the rules in TAIR can be replaced by a closed-form formulation. Then, based on the closed-form formulation, we proposed two novel techniques to further improve the testability analysis results. Our experimental results have shown improvement over the results of TAIR.