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[Author] Shih-Chieh CHANG(2hit)

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  • Novel Techniques for Improving Testability Analysis

    Yin-He SU  Ching-Hwa CHENG  Shih-Chieh CHANG  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E85-A No:12
      Page(s):
    2901-2912

    The purpose of a testability analysis program is to estimate the difficulty of testing a fault. A good measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Among those, the Controllability and Observability Procedure COP can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy in COP is due to the ignorance of signal correlations. Recently, the algorithm of TAIR in [5] proposes a testability analysis algorithm, which starts from the result of COP and then gradually improves the result by applying a set of rules. The set of rules in TAIR can capture some signal correlations and therefore the results of TAIR are more accurate than COP. In this paper, we first prove that the rules in TAIR can be replaced by a closed-form formulation. Then, based on the closed-form formulation, we proposed two novel techniques to further improve the testability analysis results. Our experimental results have shown improvement over the results of TAIR.

  • Synthesis for Multiple Input Wire Replacement of a Gate: Theorems and Applications

    Shih-Chieh CHANG  Zhong-Zhen WU  Sheng-Hong TU  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E84-A No:12
      Page(s):
    3116-3124

    The single wire replacement attempts to replace a target wire by another wire without changing the circuit functionality. Due to the large searching space required, there is very little success in directly extending the single wire replacement technique to replace multiple wires at the same time. The objective in this paper is to propose a new logic transformation, called the alternative node (Alnode) technique, which attempts to replace multiple wires at a time. Basically, the transformation simultaneously replaces multiple input wires of a gate by a new set of input wires. To accomplish the transformation, we propose several speedup theorems for replacing multiple wires. In this paper, we also demonstrate that the Alnode technique can be applied to achieve power reduction for domino logic and wire length minimization in layouts. The experimental results are encouraging.