In this paper the development of the control plane for the frame decoding functionality of an IEEE 802.16 Wireless MAN system is described. It is implemented in two ways. The first implementation is based on a general-purpose microprocessor, and specifically the one provided in the TMS320C64xx Texas family devices. The second implementation is based on an Intel's IXP2400 Network Processor chip and the preceding functions are implemented by writing embedded software for that part. The two implementations are compared and the comparison leads to some very useful results. The development of time critical tasks of a MAC protocol stack in software and mainly based on a Network Processor opens paths for very effective system architectures, where the Network Processor runs full the networking and the MAC/DLC processing of such telecom systems. The main question is: Can lower MAC be executed on a Network Processor or not? This manuscript attempts to give an answer to this question.

The architecture and implementation of a novel processor suitable wireless terminal applications, is introduced. The wireless terminal is based on the novel dual-mode baseband processor for DECT and GSM, which supports both heterodyne and direct conversion terminal architectures and is capable to undertake all baseband signal processing, and an innovative direct conversion low power modulator/demodulator for DECT and GSM. The state of the art design methodologies for embedded applications and innovative low-power design steps followed for a single chip solution. The performance of the implemented dual mode direct conversion wireless terminal was tested and measured for compliance to the standards. The developed innovative terminal fulfils all the requirements and specifications imposed by the DECT and GSM standards.

In this paper the development of the prototyping platform of a partly reconfigurable System-on-Chip (SoC) for wireless LANs, is described. It is designed to realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The current version of the system includes Mobile Terminal and AP functionality only for indoor use. Future firmware versions (configurations for its reconfigurable part) will upgrade system's functionality to allow its operation in outdoor environments and in wireless point-to-point links. The target System-on-Chip implementation platform will include instruction set processor cores, ASIC blocks and embedded reconfigurable blocks to achieve an optimal balance between implementation efficiency (area, power, performance) and flexibility. The system's prototype is developed on the ARM integrator platform and all firmware versions will be verified before ASIC prototyping.