Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip

Spyridon BLIONAS; Konstantinos MASSELOS; Chrissavgi DRE; Christos DROSOS; Fragkiskos IEROMNIMON; Dimitris METAFAS; Thanasis PAGONIS; Aristodemos PNEVMATIKAKIS; Anna TATSAKI; Theodor TRIMIS; Adamandios VONTZALIDIS

Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip

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In this paper the development of the prototyping platform of a partly reconfigurable System-on-Chip (SoC) for wireless LANs, is described. It is designed to realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The current version of the system includes Mobile Terminal and AP functionality only for indoor use. Future firmware versions (configurations for its reconfigurable part) will upgrade system's functionality to allow its operation in outdoor environments and in wireless point-to-point links. The target System-on-Chip implementation platform will include instruction set processor cores, ASIC blocks and embedded reconfigurable blocks to achieve an optimal balance between implementation efficiency (area, power, performance) and flexibility. The system's prototype is developed on the ARM integrator platform and all firmware versions will be verified before ASIC prototyping.

Publication: IEICE TRANSACTIONS on Information Vol.E86-D No.5 pp.891-900

Publication Date: 2003/05/01

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Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing)

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Spyridon BLIONAS, Konstantinos MASSELOS, Chrissavgi DRE, Christos DROSOS, Fragkiskos IEROMNIMON, Dimitris METAFAS, Thanasis PAGONIS, Aristodemos PNEVMATIKAKIS, Anna TATSAKI, Theodor TRIMIS, Adamandios VONTZALIDIS, "Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip" in IEICE TRANSACTIONS on Information, vol. E86-D, no. 5, pp. 891-900, May 2003, doi: .
Abstract: In this paper the development of the prototyping platform of a partly reconfigurable System-on-Chip (SoC) for wireless LANs, is described. It is designed to realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The current version of the system includes Mobile Terminal and AP functionality only for indoor use. Future firmware versions (configurations for its reconfigurable part) will upgrade system's functionality to allow its operation in outdoor environments and in wireless point-to-point links. The target System-on-Chip implementation platform will include instruction set processor cores, ASIC blocks and embedded reconfigurable blocks to achieve an optimal balance between implementation efficiency (area, power, performance) and flexibility. The system's prototype is developed on the ARM integrator platform and all firmware versions will be verified before ASIC prototyping.
URL: https://global.ieice.org/en_transactions/information/10.1587/e86-d_5_891/_p

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@ARTICLE{e86-d_5_891,
author={Spyridon BLIONAS, Konstantinos MASSELOS, Chrissavgi DRE, Christos DROSOS, Fragkiskos IEROMNIMON, Dimitris METAFAS, Thanasis PAGONIS, Aristodemos PNEVMATIKAKIS, Anna TATSAKI, Theodor TRIMIS, Adamandios VONTZALIDIS, },
journal={IEICE TRANSACTIONS on Information},
title={Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip},
year={2003},
volume={E86-D},
number={5},
pages={891-900},
abstract={In this paper the development of the prototyping platform of a partly reconfigurable System-on-Chip (SoC) for wireless LANs, is described. It is designed to realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The current version of the system includes Mobile Terminal and AP functionality only for indoor use. Future firmware versions (configurations for its reconfigurable part) will upgrade system's functionality to allow its operation in outdoor environments and in wireless point-to-point links. The target System-on-Chip implementation platform will include instruction set processor cores, ASIC blocks and embedded reconfigurable blocks to achieve an optimal balance between implementation efficiency (area, power, performance) and flexibility. The system's prototype is developed on the ARM integrator platform and all firmware versions will be verified before ASIC prototyping.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip
T2 - IEICE TRANSACTIONS on Information
SP - 891
EP - 900
AU - Spyridon BLIONAS
AU - Konstantinos MASSELOS
AU - Chrissavgi DRE
AU - Christos DROSOS
AU - Fragkiskos IEROMNIMON
AU - Dimitris METAFAS
AU - Thanasis PAGONIS
AU - Aristodemos PNEVMATIKAKIS
AU - Anna TATSAKI
AU - Theodor TRIMIS
AU - Adamandios VONTZALIDIS
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2003
AB - In this paper the development of the prototyping platform of a partly reconfigurable System-on-Chip (SoC) for wireless LANs, is described. It is designed to realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The current version of the system includes Mobile Terminal and AP functionality only for indoor use. Future firmware versions (configurations for its reconfigurable part) will upgrade system's functionality to allow its operation in outdoor environments and in wireless point-to-point links. The target System-on-Chip implementation platform will include instruction set processor cores, ASIC blocks and embedded reconfigurable blocks to achieve an optimal balance between implementation efficiency (area, power, performance) and flexibility. The system's prototype is developed on the ARM integrator platform and all firmware versions will be verified before ASIC prototyping.
ER -