The ITU-T J.83 Annex B is a widely adopted standard in North America for digital video and audio transmission over coaxial cable. This paper proposes a new parallel processing architecture of the parity checksum generator and syndrome generator specified in the standard for packet synchronization and error detection. The proposed parallel processing architecture removes the performance bottleneck occurring in the conventional serial processing architecture, leading to significant decrease in processing time for generating a parity checksum in transmitter and a syndrome in receiver. Implementation results show that the proposed parallel processing architecture reduces the processing time by 92% for parity checksum generation and by 81% for syndrome generation over the conventional serial processing architecture.