The search functionality is under construction.

Author Search Result

[Author] Feng RAN(2hit)

1-2hit
  • Compression Scan Strategy For Fast Refresh Rate on SXGA OLEDoS Microdisplay

    Aiying GUO  Feng RAN  Jianhua ZHANG  

     
    PAPER-Electronic Circuits

      Pubricized:
    2021/02/26
      Vol:
    E104-C No:9
      Page(s):
    455-462

    In order to upgrade the refresh rate about High-Resolution (1280×1024) OLED-on-Silicon (OLEDoS) microdisplay, this paper discusses one compression scan strategy by reducing scan time redundancy. This scan strategy firstly compresses the low-bit gray level scan serial as one unit; second, the scan unit is embedded into the high-bit gray level serial and new scan sequence is generated. Furthermore, micro-display platform is designed to verify the scan strategy performance. The experiment shows that this scan strategy can deal with 144Hz refresh rate, which is obviously faster than the traditional scan strategy.

  • Low Cost and Fault Tolerant Parallel Computing Using Stochastic Two-Dimensional Finite State Machine

    Xuechun WANG  Yuan JI  Wendong CHEN  Feng RAN  Aiying GUO  

     
    LETTER-Architecture

      Pubricized:
    2017/07/18
      Vol:
    E100-D No:12
      Page(s):
    2866-2870

    Hardware implementation of neural networks usually have high computational complexity that increase exponentially with the size of a circuit, leading to more uncertain and unreliable circuit performance. This letter presents a novel Radial Basis Function (RBF) neural network based on parallel fault tolerant stochastic computing, in which number is converted from deterministic domain to probabilistic domain. The Gaussian RBF for middle layer neuron is implemented using stochastic structure that reduce the hardware resources significantly. Our experimental results from two pattern recognition tests (the Thomas gestures and the MIT faces) show that the stochastic design is capable to maintain equivalent performance when the stream length set to 10Kbits. The stochastic hidden neuron uses only 1.2% hardware resource compared with the CORDIC algorithm. Furthermore, the proposed algorithm is very flexible in design tradeoff between computing accuracy, power consumption and chip area.