1-1hit |
Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU
In this paper, the power dissipation issue is considered in the gate sizing procedure. In order to observe the tradeoff among area, delar and power dissipation in a circuit, gate sizing algorithms which can minimize power under delay constraints or minimize area under power and delay constraints are formulated. Experiments are performed to investigate the properties of area–power–delay tradeoff in the gate sizing procedure.