This paper presents the design of a modulated complex lapped transform (MCLT) processor and its complex programmable logic device (CPLD) implementation. The MCLT is a 2x oversampled DFT filter bank; it performs well in applications that require a complex filter bank, such as noise reduction and acoustic echo cancellation. First, we show that the MCLT can be mapped to a Fast Fourier Transform (FFT). Then efficient implementation for fast MCLT computation is realized on the CPLD hardware using pipelining techniques. Detailed circuit design for the MLCT processor is presented, as well as timing diagrams for design verification and performance evaluation.