IEICE TRANSACTIONS on Fundamentals
Design and Efficient Implementation of a Modulated Complex Lapped Transform Processor Using Pipelining Technique
Summary :
This paper presents the design of a modulated complex lapped transform (MCLT) processor and its complex programmable logic device (CPLD) implementation. The MCLT is a 2x oversampled DFT filter bank; it performs well in applications that require a complex filter bank, such as noise reduction and acoustic echo cancellation. First, we show that the MCLT can be mapped to a Fast Fourier Transform (FFT). Then efficient implementation for fast MCLT computation is realized on the CPLD hardware using pipelining techniques. Detailed circuit design for the MLCT processor is presented, as well as timing diagrams for design verification and performance evaluation.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.5 pp.1280-1287
- Publication Date
- 2001/05/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Digital Signal Processing
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Heng-Ming TAI, Changyou JING, "Design and Efficient Implementation of a Modulated Complex Lapped Transform Processor Using Pipelining Technique" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 5, pp. 1280-1287, May 2001, doi: .
Abstract: This paper presents the design of a modulated complex lapped transform (MCLT) processor and its complex programmable logic device (CPLD) implementation. The MCLT is a 2x oversampled DFT filter bank; it performs well in applications that require a complex filter bank, such as noise reduction and acoustic echo cancellation. First, we show that the MCLT can be mapped to a Fast Fourier Transform (FFT). Then efficient implementation for fast MCLT computation is realized on the CPLD hardware using pipelining techniques. Detailed circuit design for the MLCT processor is presented, as well as timing diagrams for design verification and performance evaluation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_5_1280/_p
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@ARTICLE{e84-a_5_1280,
author={Heng-Ming TAI, Changyou JING, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and Efficient Implementation of a Modulated Complex Lapped Transform Processor Using Pipelining Technique},
year={2001},
volume={E84-A},
number={5},
pages={1280-1287},
abstract={This paper presents the design of a modulated complex lapped transform (MCLT) processor and its complex programmable logic device (CPLD) implementation. The MCLT is a 2x oversampled DFT filter bank; it performs well in applications that require a complex filter bank, such as noise reduction and acoustic echo cancellation. First, we show that the MCLT can be mapped to a Fast Fourier Transform (FFT). Then efficient implementation for fast MCLT computation is realized on the CPLD hardware using pipelining techniques. Detailed circuit design for the MLCT processor is presented, as well as timing diagrams for design verification and performance evaluation.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - Design and Efficient Implementation of a Modulated Complex Lapped Transform Processor Using Pipelining Technique
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1280
EP - 1287
AU - Heng-Ming TAI
AU - Changyou JING
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2001
AB - This paper presents the design of a modulated complex lapped transform (MCLT) processor and its complex programmable logic device (CPLD) implementation. The MCLT is a 2x oversampled DFT filter bank; it performs well in applications that require a complex filter bank, such as noise reduction and acoustic echo cancellation. First, we show that the MCLT can be mapped to a Fast Fourier Transform (FFT). Then efficient implementation for fast MCLT computation is realized on the CPLD hardware using pipelining techniques. Detailed circuit design for the MLCT processor is presented, as well as timing diagrams for design verification and performance evaluation.
ER -
English
