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[Author] Heng-Yu CHEN(2hit)

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  • An Efficient Initialization Scheme for SOM Algorithm Based on Reference Point and Filters

    Shu-Ling SHIEH  I-En LIAO  Kuo-Feng HWANG  Heng-Yu CHEN  

     
    PAPER-Data Mining

      Vol:
    E92-D No:3
      Page(s):
    422-432

    This paper proposes an efficient self-organizing map algorithm based on reference point and filters. A strategy called Reference Point SOM (RPSOM) is proposed to improve SOM execution time by means of filtering with two thresholds T1 and T2. We use one threshold, T1, to define the search boundary parameter used to search for the Best-Matching Unit (BMU) with respect to input vectors. The other threshold, T2, is used as the search boundary within which the BMU finds its neighbors. The proposed algorithm reduces the time complexity from O(n2) to O(n) in finding the initial neurons as compared to the algorithm proposed by Su et al. [16] . The RPSOM dramatically reduces the time complexity, especially in the computation of large data set. From the experimental results, we find that it is better to construct a good initial map and then to use the unsupervised learning to make small subsequent adjustments.

  • CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes

    Hong-Yi HUANG  Shiun-Dian JAN  Yang CHOU  Cheng-Yu CHEN  

     
    PAPER-Electronic Circuits

      Vol:
    E95-C No:2
      Page(s):
    275-283

    The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.