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Hiromi NOBUKATA Kenichi SATORI Shinji HIRAMATSU Hideki ARAKAWA
An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.