A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture
Summary :
An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.818-824
- Publication Date
- 1995/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
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Hiromi NOBUKATA, Kenichi SATORI, Shinji HIRAMATSU, Hideki ARAKAWA, "A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 7, pp. 818-824, July 1995, doi: .
Abstract: An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_7_818/_p
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@ARTICLE{e78-c_7_818,
author={Hiromi NOBUKATA, Kenichi SATORI, Shinji HIRAMATSU, Hideki ARAKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture},
year={1995},
volume={E78-C},
number={7},
pages={818-824},
abstract={An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 818
EP - 824
AU - Hiromi NOBUKATA
AU - Kenichi SATORI
AU - Shinji HIRAMATSU
AU - Hideki ARAKAWA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.
ER -
English
