We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.

In this paper we introduce a CMOS low voltage/low power (LV/LP) voltage controlled oscillator (VCO). It includes a simple V-I converter, a current controlled ring oscillator based on new differential delay cells, and a source-coupled differential pair to convert differential signal to single-ended signal. The V-I converter is implemented as a source follower type, exhibiting excellent linearity of transconductance with low power consumption. The new delay cell employs local positive feedback to increase its DC gain, achieving stable oscillation at low supply voltage. The simulation and measurement results are given to show the linearity between the input (control voltage) and the output (frequency) in the frequency range of 100 MHz to 400 MHz with 1. 2 V power supply. The VCO only consumes power of 2.25 mW at operating frequency of 400 MHz and 1.2 V supply.