IEICE TRANSACTIONS on Electronics
Low Supply Voltage and Low-Power 1-GHz PLL Frequency Synthesizer for Mobile Terminals
Summary :
We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.1 pp.71-78
- Publication Date
- 2003/01/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Masaru KOKUBO, Yoshiyuki SHIBAHARA, Hirokazu AOKI, Changku HWANG, "Low Supply Voltage and Low-Power 1-GHz PLL Frequency Synthesizer for Mobile Terminals" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 1, pp. 71-78, January 2003, doi: .
Abstract: We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_1_71/_p
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@ARTICLE{e86-c_1_71,
author={Masaru KOKUBO, Yoshiyuki SHIBAHARA, Hirokazu AOKI, Changku HWANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Supply Voltage and Low-Power 1-GHz PLL Frequency Synthesizer for Mobile Terminals},
year={2003},
volume={E86-C},
number={1},
pages={71-78},
abstract={We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - Low Supply Voltage and Low-Power 1-GHz PLL Frequency Synthesizer for Mobile Terminals
T2 - IEICE TRANSACTIONS on Electronics
SP - 71
EP - 78
AU - Masaru KOKUBO
AU - Yoshiyuki SHIBAHARA
AU - Hirokazu AOKI
AU - Changku HWANG
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2003
AB - We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.
ER -
English
