This paper presents a high resolution mixed-domain Delta-Sigma (ΔΣ) time-to-digital converter (TDC) which utilizes a charge pump as time-to-voltage converter, a low resolution SAR ADC as quantizer, and a pair of delay-line digital-to-time converters to form a negative feedback. By never resetting the sampling capacitor of the charge-pump, an integrator is realized and first order noise shaping can be achieved. However, since the integrating capacitor is never cleared, this circuit is prone to charge-sharing issue during input sampling which can degrade TDC's performance. To deal with this issue, a compensation circuit consists of another pair of sampling capacitors and charge-pumps with doubled current is proposed. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 2.5 MHz bandwidth, simulation shows that this TDC achieves 66.4 dB SNDR and 295 fsrms integrated noise for ±1 ns input range. The proposed TDC consumes 1.78 mW power that translates to FoM of 208 fJ/conv.

In this paper, we derive state equations for linearized discrete-time models of forth-order charge-pump phase-locked loops. We solve the differential equations of the loop filter by using the initial conditions and the boundary conditions in a period. The solved equations are linearized and rearranged as discrete-time state equations for checking stability conditions. Some behavioral simulations are performed to verify the proposed method. By examining the stability of loops with different conditions, we also propose an expression between the lower bound of the reference frequency, the open loop unit gain bandwidth, and the phase margin.

We have developed a high-efficiency charge-pump power supply circuit with large output current capability for mobile equipment. However, during the commercialization phase, we found that the large inrush current of 270 mA at charge-pump circuit startup-time could cause problems. In this paper we analyze the mechanism that causes this inrush current, and we propose circuitry to reduce it. We show SPICE simulation and measurement results for our proposed circuitry that confirm its effectiveness. By incorporating this circuitry, startup-time inrush current was reduced to 30 mA.

This paper presents a 0.5Vdd-step pumping method for Dickson-type charge-pump circuits that achieve high overall efficiency, including regulator circuitry, even at large output currents, and these circuits are targeted at mobile equipment applications. We have designed positive and negative charge-pump circuits which use a 0.5Vdd-step pumping method, are implemented with advanced control functions, and are fabricated with our custom CMOS process. Measured results showed that efficiency of a 2.5-stage positive charge-pump circuit before regulation is more than 93% (power supply Vdd=5 V, output voltage Vout=16.9 V 3.5Vdd, output current Iout=4 mA), and that of a 1.5-stage negative charge-pump circuit is 93% (power supply Vdd=5 V, output voltage Vout=-7.2 V -1.5Vdd, output current Iout=4 mA).

We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.

This paper presents improved versions of three-stage positive-output and two-stage negative-output Dickson charge-pump circuits which are intended to replace switching regulators in video-product CCD driver applications (where 12 V and -6.5 V are needed), and are designed and fabricated in a custom CMOS process. From a power supply Vdd of 4.0 to 5.5 V, the positive charge pump generates a positive output voltage of greater than 3.9Vdd, while the negative charge pump generates a negative voltage of greater than -1.9Vdd, both with efficiencies of greater than 94% at 2 mA output currents.

In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.

In this paper, we analyze overload and stability in the charge-pump phase locked loop (PLL). We propose a new computational model that can be applied for the precise estimation of the physical limits of charge-pump, the leakage current of loop filter and waveform distortion of charge-pump PLL operating in high speed. We derive the exact mathematical expressions of the parameters describing the steady-state behavior of the PLL as well as the transient-state behavior. Performance comparisons with the conventional model are provided through numerical results. Algorithms for approximate analysis is also provided. The new model is particularity useful for analyzing the cases that the charge-pump PLL operates in high- speed or the loop filter has large leakage current.