On-chip testing for 30 K-gate masterslice with freely configured SRAM AND/OR ROM blocks was investigated. Multiplier fault coverage was about 93 percent. The validity of on-chip testing was confirmed in masterslices containing over 20 K gates with memory blocks.

A 5.6 GOPS/1.4 GFLOPS 350 MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18 µm five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and media pipeline has two-parallel and four-parallel single instruction multiple-data (SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16 KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7 million transistors are integrated in an area of 7.5 mm 7.5 mm. Since all circuit blocks were developed using logic synthesis, the processor is easy to adapt to system-on-a-chip (SoC) applications.

A 12.8GOPS/2.1GFLOPS that operates at 533 MHz, and which is equipped with an 8-way embedded VLIW processor fabricated with 6-layer Cu and 1-layer Al metal 0.11 µm CMOS process technology is introduced in this paper. The processor is also equipped with a 4-way integer pipeline, a 4-way floating/media pipeline, and separate 32 KB 4-way set associative instruction and data caches. It is also equipped with instruction fetch prediction, and non-aligned dual data load/store mechanisms. The performance evaluation that was successfully conducted using the MPEG2 IDCT routine and JPEG decoding program shows that it offers twice the performance of the previous work . 10.4 M transistors are integrated on a 7.8 mm 7.8 mm die. The chip consumes 2.5 W at 533 MHz.