This paper describes a 1-Mb (256K 4) CMOS SRAM with 6-ns access time. The SRAM, having a cell size of 3.8 µm 7.2 µm and a die size of 6.09 mm 12.94 mm, is fabricated using 0.5-µm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new nMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle.