A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier

Teruo SEKI; Eisaku ITOH; Chiaki FURUKAWA; Isamu MAENO; Tadashi OZAWA; Hiroyuki SANO; Noriyuki SUZUKI

A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier

Teruo SEKI, Eisaku ITOH, Chiaki FURUKAWA, Isamu MAENO, Tadashi OZAWA, Hiroyuki SANO, Noriyuki SUZUKI

Full Text Views

0

Cite this

Summary :

This paper describes a 1-Mb (256K 4) CMOS SRAM with 6-ns access time. The SRAM, having a cell size of 3.8 µm 7.2 µm and a die size of 6.09 mm 12.94 mm, is fabricated using 0.5-µm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new nMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.5 pp.818-823

Publication Date: 1993/05/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))

Category

Authors

Teruo SEKI
Eisaku ITOH
Chiaki FURUKAWA
Isamu MAENO
Tadashi OZAWA
Hiroyuki SANO
Noriyuki SUZUKI

Keyword

Cite this

Copy

Teruo SEKI, Eisaku ITOH, Chiaki FURUKAWA, Isamu MAENO, Tadashi OZAWA, Hiroyuki SANO, Noriyuki SUZUKI, "A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 5, pp. 818-823, May 1993, doi: .
Abstract: This paper describes a 1-Mb (256K 4) CMOS SRAM with 6-ns access time. The SRAM, having a cell size of 3.8 µm 7.2 µm and a die size of 6.09 mm 12.94 mm, is fabricated using 0.5-µm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new nMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_5_818/_p

Copy

@ARTICLE{e76-c_5_818,
author={Teruo SEKI, Eisaku ITOH, Chiaki FURUKAWA, Isamu MAENO, Tadashi OZAWA, Hiroyuki SANO, Noriyuki SUZUKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier},
year={1993},
volume={E76-C},
number={5},
pages={818-823},
abstract={This paper describes a 1-Mb (256K 4) CMOS SRAM with 6-ns access time. The SRAM, having a cell size of 3.8 µm 7.2 µm and a die size of 6.09 mm 12.94 mm, is fabricated using 0.5-µm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new nMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle.},
keywords={},
doi={},
ISSN={},
month={May},}

Copy

TY - JOUR
TI - A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier
T2 - IEICE TRANSACTIONS on Electronics
SP - 818
EP - 823
AU - Teruo SEKI
AU - Eisaku ITOH
AU - Chiaki FURUKAWA
AU - Isamu MAENO
AU - Tadashi OZAWA
AU - Hiroyuki SANO
AU - Noriyuki SUZUKI
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1993
AB - This paper describes a 1-Mb (256K 4) CMOS SRAM with 6-ns access time. The SRAM, having a cell size of 3.8 µm 7.2 µm and a die size of 6.09 mm 12.94 mm, is fabricated using 0.5-µm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new nMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle.
ER -