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[Author] Hung-Wei CHEN(2hit)

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  • A Precision CMOS Power-On-Reset Circuit with Power Noise Immunity for Low-Voltage Technology

    Wen-Cheng YEN  Hung-Wei CHEN  Yu-Tong LIN  

     
    PAPER-Electronic Circuits

      Vol:
    E87-C No:5
      Page(s):
    778-784

    In this era of System-On-a-Chip (SOC) technology, a designable initial state is required. Thus, embedding low voltage and low power Power-On-Reset (POR) circuit on the SOC chip is important for the portable device. This paper proposes a new POR circuit with process and temperature compensations. A band-gap reference is used in this circuit to reduce the effect of the temperature and process variations. With 200 mV hysteretic design provides robust noise immunity against voltage fluctuations on the power supply. The POR circuit has been designed, simulated, and implemented. A test chip has been fabricated by using 0.18 µm single-poly triple-metal CMOS logical process. Measurement results show the rise threshold voltage Vrr has only a 3% variation under the temperature range from -40 to 125. The power consumption is 39 mW at the 1.8 V power supply. The chip size of the POR is 62 mm280 mm. Thus, this POR circuit has a great potential to apply to a low power supply system.

  • A Spread Spectrum Clock Generator for EMI Reduction

    Hung-Wei CHEN  Jiin-Chuan WU  

     
    PAPER-Integrated Electronics

      Vol:
    E84-C No:12
      Page(s):
    1959-1966

    This paper described a new method to generate a spread spectrum clock for the purpose of EMI reduction. This method uses two phase-locked loops (PLL). The output of the first PLL is locked to its input of 14.318 MHz. The VCO in this PLL is used to produce 32 outputs with the same frequency and each with 11.25 degrees phase variation. A digital spread spectrum generator uses these 32 signals to generate the desired spread spectrum signal by phase hopping technique. These two circuits form a spread spectrum digital PLL (SSDPLL). The second PLL is configured as a conventional frequency synthesizer. It can be programmed to generate the desired frequencies. The second PLL also serves as a low pass filter of the output of the SSDPLL to smooth out frequency variation. This circuit was implemented with a 0.6 µm single poly CMOS process. The active areas of the SSDPLL and the synthesizer are 826396 µm2 and 790298 µm2, respectively. The total power consumption is 99 mW at 3.3 V supply. The peak power of the spread spectrum clock is reduced by 10 dBm at 14.318 MHz output with a 2.34% frequency spreading. The reduction of peak power increases with output frequency.