A Spread Spectrum Clock Generator for EMI Reduction

Hung-Wei CHEN; Jiin-Chuan WU

A Spread Spectrum Clock Generator for EMI Reduction

Hung-Wei CHEN, Jiin-Chuan WU

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This paper described a new method to generate a spread spectrum clock for the purpose of EMI reduction. This method uses two phase-locked loops (PLL). The output of the first PLL is locked to its input of 14.318 MHz. The VCO in this PLL is used to produce 32 outputs with the same frequency and each with 11.25 degrees phase variation. A digital spread spectrum generator uses these 32 signals to generate the desired spread spectrum signal by phase hopping technique. These two circuits form a spread spectrum digital PLL (SSDPLL). The second PLL is configured as a conventional frequency synthesizer. It can be programmed to generate the desired frequencies. The second PLL also serves as a low pass filter of the output of the SSDPLL to smooth out frequency variation. This circuit was implemented with a 0.6 µm single poly CMOS process. The active areas of the SSDPLL and the synthesizer are 826396 µm² and 790298 µm², respectively. The total power consumption is 99 mW at 3.3 V supply. The peak power of the spread spectrum clock is reduced by 10 dBm at 14.318 MHz output with a 2.34% frequency spreading. The reduction of peak power increases with output frequency.

Publication: IEICE TRANSACTIONS on Electronics Vol.E84-C No.12 pp.1959-1966

Publication Date: 2001/12/01

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Hung-Wei CHEN, Jiin-Chuan WU, "A Spread Spectrum Clock Generator for EMI Reduction" in IEICE TRANSACTIONS on Electronics, vol. E84-C, no. 12, pp. 1959-1966, December 2001, doi: .
Abstract: This paper described a new method to generate a spread spectrum clock for the purpose of EMI reduction. This method uses two phase-locked loops (PLL). The output of the first PLL is locked to its input of 14.318 MHz. The VCO in this PLL is used to produce 32 outputs with the same frequency and each with 11.25 degrees phase variation. A digital spread spectrum generator uses these 32 signals to generate the desired spread spectrum signal by phase hopping technique. These two circuits form a spread spectrum digital PLL (SSDPLL). The second PLL is configured as a conventional frequency synthesizer. It can be programmed to generate the desired frequencies. The second PLL also serves as a low pass filter of the output of the SSDPLL to smooth out frequency variation. This circuit was implemented with a 0.6 µm single poly CMOS process. The active areas of the SSDPLL and the synthesizer are 826396 µm² and 790298 µm², respectively. The total power consumption is 99 mW at 3.3 V supply. The peak power of the spread spectrum clock is reduced by 10 dBm at 14.318 MHz output with a 2.34% frequency spreading. The reduction of peak power increases with output frequency.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_12_1959/_p

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@ARTICLE{e84-c_12_1959,
author={Hung-Wei CHEN, Jiin-Chuan WU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Spread Spectrum Clock Generator for EMI Reduction},
year={2001},
volume={E84-C},
number={12},
pages={1959-1966},
abstract={This paper described a new method to generate a spread spectrum clock for the purpose of EMI reduction. This method uses two phase-locked loops (PLL). The output of the first PLL is locked to its input of 14.318 MHz. The VCO in this PLL is used to produce 32 outputs with the same frequency and each with 11.25 degrees phase variation. A digital spread spectrum generator uses these 32 signals to generate the desired spread spectrum signal by phase hopping technique. These two circuits form a spread spectrum digital PLL (SSDPLL). The second PLL is configured as a conventional frequency synthesizer. It can be programmed to generate the desired frequencies. The second PLL also serves as a low pass filter of the output of the SSDPLL to smooth out frequency variation. This circuit was implemented with a 0.6 µm single poly CMOS process. The active areas of the SSDPLL and the synthesizer are 826396 µm² and 790298 µm², respectively. The total power consumption is 99 mW at 3.3 V supply. The peak power of the spread spectrum clock is reduced by 10 dBm at 14.318 MHz output with a 2.34% frequency spreading. The reduction of peak power increases with output frequency.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Spread Spectrum Clock Generator for EMI Reduction
T2 - IEICE TRANSACTIONS on Electronics
SP - 1959
EP - 1966
AU - Hung-Wei CHEN
AU - Jiin-Chuan WU
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2001
AB - This paper described a new method to generate a spread spectrum clock for the purpose of EMI reduction. This method uses two phase-locked loops (PLL). The output of the first PLL is locked to its input of 14.318 MHz. The VCO in this PLL is used to produce 32 outputs with the same frequency and each with 11.25 degrees phase variation. A digital spread spectrum generator uses these 32 signals to generate the desired spread spectrum signal by phase hopping technique. These two circuits form a spread spectrum digital PLL (SSDPLL). The second PLL is configured as a conventional frequency synthesizer. It can be programmed to generate the desired frequencies. The second PLL also serves as a low pass filter of the output of the SSDPLL to smooth out frequency variation. This circuit was implemented with a 0.6 µm single poly CMOS process. The active areas of the SSDPLL and the synthesizer are 826396 µm² and 790298 µm², respectively. The total power consumption is 99 mW at 3.3 V supply. The peak power of the spread spectrum clock is reduced by 10 dBm at 14.318 MHz output with a 2.34% frequency spreading. The reduction of peak power increases with output frequency.
ER -