This paper introduces a new method of deriving high-speed FFT based on two-dimensional parallel processing, and describes its VLSI hardware implementation. With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. Among them, subjects concerning the development of a new FFT algorithm to handle extremely large volumes of data, and the design of special hardware using that algorithm are pointed out. This paper proposes a two-dimensional systolic array hardware structure and also proposes a new computing algorithm for performing data permutation by a two-dimensional systolic array to solve the above stated problem. The proposed array structure and the algorithm provide highly parallel processing suited for high speed FFT on a large number of data. In addition, a new algorithm to process arbitrary sampling points without hardware modification is suggested. Finally, the comparison of performance among the proposed FFT method by two-dimensional systolic array, systolic DFT array proposed by Kung and the existing general unity FFT processor is investigated.