IEICE TRANSACTIONS on transactions
Parallel Processing FFT for VLSI Implementation
Summary :
This paper introduces a new method of deriving high-speed FFT based on two-dimensional parallel processing, and describes its VLSI hardware implementation. With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. Among them, subjects concerning the development of a new FFT algorithm to handle extremely large volumes of data, and the design of special hardware using that algorithm are pointed out. This paper proposes a two-dimensional systolic array hardware structure and also proposes a new computing algorithm for performing data permutation by a two-dimensional systolic array to solve the above stated problem. The proposed array structure and the algorithm provide highly parallel processing suited for high speed FFT on a large number of data. In addition, a new algorithm to process arbitrary sampling points without hardware modification is suggested. Finally, the comparison of performance among the proposed FFT method by two-dimensional systolic array, systolic DFT array proposed by Kung and the existing general unity FFT processor is investigated.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E68-E No.5 pp.284-291
- Publication Date
- 1985/05/25
- Publicized
- Online ISSN
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- Type of Manuscript
- PAPER
- Category
- Computers
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Hyon Soo LEE, Hideki MORI, Hideo AISO, "Parallel Processing FFT for VLSI Implementation" in IEICE TRANSACTIONS on transactions,
vol. E68-E, no. 5, pp. 284-291, May 1985, doi: .
Abstract: This paper introduces a new method of deriving high-speed FFT based on two-dimensional parallel processing, and describes its VLSI hardware implementation. With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. Among them, subjects concerning the development of a new FFT algorithm to handle extremely large volumes of data, and the design of special hardware using that algorithm are pointed out. This paper proposes a two-dimensional systolic array hardware structure and also proposes a new computing algorithm for performing data permutation by a two-dimensional systolic array to solve the above stated problem. The proposed array structure and the algorithm provide highly parallel processing suited for high speed FFT on a large number of data. In addition, a new algorithm to process arbitrary sampling points without hardware modification is suggested. Finally, the comparison of performance among the proposed FFT method by two-dimensional systolic array, systolic DFT array proposed by Kung and the existing general unity FFT processor is investigated.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e68-e_5_284/_p
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@ARTICLE{e68-e_5_284,
author={Hyon Soo LEE, Hideki MORI, Hideo AISO, },
journal={IEICE TRANSACTIONS on transactions},
title={Parallel Processing FFT for VLSI Implementation},
year={1985},
volume={E68-E},
number={5},
pages={284-291},
abstract={This paper introduces a new method of deriving high-speed FFT based on two-dimensional parallel processing, and describes its VLSI hardware implementation. With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. Among them, subjects concerning the development of a new FFT algorithm to handle extremely large volumes of data, and the design of special hardware using that algorithm are pointed out. This paper proposes a two-dimensional systolic array hardware structure and also proposes a new computing algorithm for performing data permutation by a two-dimensional systolic array to solve the above stated problem. The proposed array structure and the algorithm provide highly parallel processing suited for high speed FFT on a large number of data. In addition, a new algorithm to process arbitrary sampling points without hardware modification is suggested. Finally, the comparison of performance among the proposed FFT method by two-dimensional systolic array, systolic DFT array proposed by Kung and the existing general unity FFT processor is investigated.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Parallel Processing FFT for VLSI Implementation
T2 - IEICE TRANSACTIONS on transactions
SP - 284
EP - 291
AU - Hyon Soo LEE
AU - Hideki MORI
AU - Hideo AISO
PY - 1985
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E68-E
IS - 5
JA - IEICE TRANSACTIONS on transactions
Y1 - May 1985
AB - This paper introduces a new method of deriving high-speed FFT based on two-dimensional parallel processing, and describes its VLSI hardware implementation. With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. Among them, subjects concerning the development of a new FFT algorithm to handle extremely large volumes of data, and the design of special hardware using that algorithm are pointed out. This paper proposes a two-dimensional systolic array hardware structure and also proposes a new computing algorithm for performing data permutation by a two-dimensional systolic array to solve the above stated problem. The proposed array structure and the algorithm provide highly parallel processing suited for high speed FFT on a large number of data. In addition, a new algorithm to process arbitrary sampling points without hardware modification is suggested. Finally, the comparison of performance among the proposed FFT method by two-dimensional systolic array, systolic DFT array proposed by Kung and the existing general unity FFT processor is investigated.
ER -
English
