The key weakness of Low-Density Parity Check codes is the complexity of the encoding scheme. The generator matrices can be made by Gaussian elimination of parity check matrices for normal block codes. Richardson succeeded in making parity bits from parity check matrices by the low density computation. In this letter, we focus on the execution of numerical experiments which show that even if the matrix D, which is the part of the Richardson's LDPC matrix, is restricted, proposed LDPC codes is lower complexity than Richardson's LDPC codes. The constraint of D results in reducing complexity from O(n + g2) to O(n) due to the omission of computing inverse matrices of φ and T in Richardson's encoding scheme. All the sub-matrices in parity check matrix are composed of Circulant Permutation Matrices based on Galois Fields.

The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.