IEICE TRANSACTIONS on Fundamentals
Efficient Encoding Architecture for IEEE 802.16e LDPC Codes
Summary :
The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3607-3611
- Publication Date
- 2008/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.12.3607
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Embedded, Real-Time and Reconfigurable Systems
Authors
Keyword
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Jeong Ki KIM, Hyunseuk YOO, Moon Ho LEE, "Efficient Encoding Architecture for IEEE 802.16e LDPC Codes" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3607-3611, December 2008, doi: 10.1093/ietfec/e91-a.12.3607.
Abstract: The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3607/_p
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@ARTICLE{e91-a_12_3607,
author={Jeong Ki KIM, Hyunseuk YOO, Moon Ho LEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient Encoding Architecture for IEEE 802.16e LDPC Codes},
year={2008},
volume={E91-A},
number={12},
pages={3607-3611},
abstract={The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3607},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Efficient Encoding Architecture for IEEE 802.16e LDPC Codes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3607
EP - 3611
AU - Jeong Ki KIM
AU - Hyunseuk YOO
AU - Moon Ho LEE
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3607
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.
ER -
English
