The main contribution of this work is to propose energy-efficient randomized initialization protocols for ad-hoc radio networks (ARN, for short). First, we show that if the number n of stations is known beforehand, the single-channel ARN can be initialized by a protocol that terminates, with high probability, in O(n) time slots with no station being awake for more than O(log n) time slots. We then go on to address the case where the number n of stations in the ARN is not known beforehand. We begin by discussing, an elegant protocol that provides a tight approximation of n. Interestingly, this protocol terminates, with high probability, in O((log n)2) time slots and no station has to be awake for more than O(log n) time slots. We use this protocol to design an energy-efficient initialization protocol that terminates, with high probability, in O(n) time slots with no station being awake for more than O(log n) time slots. Finally, we design an energy-efficient initialization protocol for the k-channel ARN that terminates, with high probability, in O(n/k+log n) time slots, with no station being awake for more than O(log n) time slots.

The main contribution of this work is to propose energy-efficient protocols that compute the sum of n numbers over any commutative and associative binary operator stored in n wireless sensor nodes arranged in a two-dimensional grid of size nn. We first present a protocol that computes the sum on a Wireless Sensor Network (WSN) in O(r2+(n/r2)1/3) time slots with no sensor node being awake for more than O(1) time slots, where r is the transmission range of the sensor nodes. We then go on to present a fault-tolerant protocol which computes the sum in the same number of time slots with no sensor node being awake for more than O(log r) time slots. Finally, we show that in a WSN where the sensor nodes are empowered with the ability to dynamically adjust their transmission range r during the execution of the protocol, the sum can be computed in O(log n) time slots and no sensor node needs to awake for more than O(log n) time slots.

A Radio Network (RN, for short) is a distributed system with no central arbiter, consisting of p radio stations each of which is endowed with a radio transceiver. In this work we consider single-hop, single channel RNs, where each station S(i), (1ip), initially stores si items which are tagged with the unique destination they must be routed. Since each item must be transmitted at least once, every routing protocol must take at least n = s1 + s2 + + sp time slots to route each item to its final destination. Similarly, each station S(i), (1ip), must be awake for at least si + di time slots to broadcast si items and to receive di items, where di denotes the number of items destined for S(i). The main contribution of this work is to present a randomized time- and energy-optimal routing protocol on the RN. Let qi, (1ip), be the number of stations that have items destined for S(i), q=q1 +q2 ++ qp, and ri be the number of stations for which S(i) has items. When qi is known to station S(i), our routing protocol runs, with probability exceeding 1 - , (f > 1), in n + O(q + log f) time slots with each station S(i) being awake for at most si + di + O(qi + ri + log f) time slots. Since qidi, risi, and qn always hold, our randomized routing protocol is optimal. We also show that, when the value of di is known to S(i), our routing protocol runs, with probability exceeding 1 - , (f > 1), in O(n + log f) time slots with no station being awake for more than O(si + di + log f) time slots.

Algorithms requiring fast manipulation of multiple-length numbers are usually implemented in hardware. However, hardware implementation, using HDL (Hardware Description Language) for instance, is a laborious task and the quality of the solution relies heavily on the designer expertise. The main contribution of this work is to present a flexible-length-arithmetic processor based on FDFM (Few DSP slices and Few Memory blocks) approach that supports arithmetic operations on multiple-length numbers using FPGAs (Field Programmable Gate Array). The proposed processor has been implement on the Xilinx Virtex-6 FPGA. Arithmetic instructions of the proposed processor architecture include addition, subtraction, and multiplication of integer numbers exceeding 64-bits. To reduce the burden of implementing algorithm directly on the FPGA, applications requiring multiple-length arithmetic operations are written in a C-like language and translated into a machine program. The machine program is then transferred and executed on the proposed architecture. A 2048-bit RSA encryption/decryption implementation has been used to assess the goodness of the proposed approach. Experimental results shows that the computing time, using the proposed architecture, of a 2048-bit RSA encryption takes only 2.2 times longer than a direct FPGA implementation. Furthermore, by employing multiple FDFM cores for the same task, the computing time reduces considerably.

Directional communications have been considered as a feasible alternative to improve spatial division and throughput in mobile communication environments. In general, directional MAC protocols proposed in the literature rely on channel reservation based on control frames, such as RTS/CTS. Notwithstanding, channel reservation based on control frames increases latency and has an impact on the network throughput. The main contribution of this paper is to propose a channel reservation technique based on pulse/tone signals. The proposed scheme, termed directional pulse/tone channel reservation (DPTCR), allows for efficient channel reservation without resorting to control frames such as RTS and CTS. Theoretical and empirical results show that the proposed scheme has a low probability of failure while providing significant throughput gains. The results show that DPTCR is able to provide throughput improvement up to 158% higher as compared to traditional channel reservation employing RTS/CTS frames.

In this paper we present a network layer based admission control and simple class based service differentiation model to support QoS in mobile ad hoc network. Our distributed admission control procedure works along with the route finding phase of reactive routing protocols for mobile ad hoc network (AODV, DSR etc). We also propose a simple class based distributed service differentiation system to support QoS once a traffic is admitted by our admission control mechanism. The proposed service differentiation is based on DiffServ model and includes modifications like configuration of each node with edge and core functionality, dynamic selection of edge/core functionality, use of minimal and simple classes. Simulation results show that our system allows seven times more real time traffic in the network than the proposed QoS for AODV model while satisfying the demanded end-to-end delay and providing low jitter.

The main contribution of this paper is to present an FPGA-based implementation of an instance-specific hardware which accelerates the CKY (Cocke-Kasami-Younger) parsing for context-free grammars. Given a context-free grammar G and a string x, the CKY parsing determines whether G derives x. We have developed a hardware generator that creates a Verilog HDL source to perform the CKY parsing for any given context-free grammar G. The generated source is embedded in an FPGA using the design software provided by the FPGA vendor. We evaluated the instance-specific hardware, generated by our hardware generator, using a timing analyzer and tested it using the Altera FPGAs. The generated hardware attains a speed-up factor of approximately 750 over the software CKY parsing algorithm.