This paper is concerned with radio resource allocation in multiple-chip-rate (MCR) DS/CDMA systems accommodating multimedia services with different information rates and quality requirements. Considering both power spectral density (PSD) over a radio frequency (RF) band and the effect of RF input filtering on the receiver in MCR-DS/CDMA systems, criteria for capacity estimation are presented and the characteristics of co-channel interference between subsystems are investigated. System performance in MCR-DS/CDMA systems is strongly affected by radio resource assignment. A minimum power-increment-based resource assignment scheme for an efficient resource assignment scheme is proposed herein. The performance of this scheme is compared with that of a random-based resource assignment scheme in terms of blocking probability and normalized throughput. The minimum power-increment-based resource assignment scheme yields a better performance than the random-based resource assignment scheme for multimedia services.

We propose and evaluate a single-bit adaptive step-size closed-loop power control (AS-CLPC) scheme which is adaptable to a dynamically changing radio channel. We also investigate the effect of the mobile terminal (MT) velocity on system performance when the proposed AS-CLPC scheme is employed. The proper power control constant of the AS-CLPC scheme is obtained by solving a polynomial equation. Compared with the IS-95 single-bit fixed step-size CLPC scheme, the proposed single-bit AS-CLPC scheme can reduce link margin (LM) by about 3 dB when the outage probability is below 0. 03 and a single fading path reception in the base station is assumed. System performance such as link availability and throughput can be improved by utilizing this proposed CLPC scheme in the outdoor radio propagation channel where time-selective fading occurs.

The most important function of a router is to perform IP lookup that determines the output ports of incoming IP packets by their destination addresses. Hence, IP lookup is one of the main issues in implementing high-speed routers. The IP lookup algorithm implemented in IQ2200 Chipset with two-level table architecture can efficiently use memory. However, it wastes processor resource for full re-construction of the forwarding tables whenever every route insertion/deletion is requested. In order to improve the utilization of processor resource, we propose an IP lookup algorithm with three-level table architecture for high-speed routers. We evaluate the performance of the proposed algorithm in terms of the memory size required for storing lookup information and the number of memory access in constructing forwarding tables. Being compared with the IQ2200 scheme, the proposed scheme can reduce the number of memory access up to 99% even though it needs about 16% more memory.