Differential power analysis (DPA) is an effective technique that extracts secret keys from cryptographic systems through statistical analysis of the power traces obtained during encryption and decryption operations. This letter proposes symmetric discharge logic (SDL), a circuit-level countermeasure against DPA, which exhibits uniform power traces for every clock period by maintaining a set of discharge paths independent of input values. This feature minimizes differences in power traces and improves resistance to DPA attacks. HSPICE simulations for the test circuits using 0.18 µm TSMC CMOS process parameters indicate that SDL reduces power differences by an order of magnitude, compared to the existing circuit-level technique.

This letter proposes an efficient method to find the optimum subfield code, which minimizes the visual artifacts on the motion pictures of the plasma display panel (PDP). Existing codes were constructed to reduce dynamic false contour (DFC) only, and they are fixed codes used for every image. In contrast, the proposed method aims to minimize the total artifacts by DFC and halftone noise (HN), and it finds the best code for a given image, dynamically. First, this letter presents the novel models to estimate the effect of DFC and HN for given codewords and a given image. Then, it presents an efficient method that finds the optimum code for a given image using the well-known shortest-path algorithm. Experimental results, using 459 HDTV images, illustrated that the proposed approach improved the average PSNR by 0.713 dB and 7.004 dB in DFC and HN, respectively, when compared with Gravity Centre Code [1].