Symmetric Discharge Logic against Differential Power Analysis

Jong Suk LEE; Jae Woon LEE; Young Hwan KIM

doi:10.1093/ietfec/e90-a.1.234

Symmetric Discharge Logic against Differential Power Analysis

Jong Suk LEE, Jae Woon LEE, Young Hwan KIM

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Differential power analysis (DPA) is an effective technique that extracts secret keys from cryptographic systems through statistical analysis of the power traces obtained during encryption and decryption operations. This letter proposes symmetric discharge logic (SDL), a circuit-level countermeasure against DPA, which exhibits uniform power traces for every clock period by maintaining a set of discharge paths independent of input values. This feature minimizes differences in power traces and improves resistance to DPA attacks. HSPICE simulations for the test circuits using 0.18 µm TSMC CMOS process parameters indicate that SDL reduces power differences by an order of magnitude, compared to the existing circuit-level technique.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.1 pp.234-240

Publication Date: 2007/01/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.1.234

Type of Manuscript: Special Section LETTER (Special Section on Cryptography and Information Security)

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Jong Suk LEE, Jae Woon LEE, Young Hwan KIM, "Symmetric Discharge Logic against Differential Power Analysis" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 1, pp. 234-240, January 2007, doi: 10.1093/ietfec/e90-a.1.234.
Abstract: Differential power analysis (DPA) is an effective technique that extracts secret keys from cryptographic systems through statistical analysis of the power traces obtained during encryption and decryption operations. This letter proposes symmetric discharge logic (SDL), a circuit-level countermeasure against DPA, which exhibits uniform power traces for every clock period by maintaining a set of discharge paths independent of input values. This feature minimizes differences in power traces and improves resistance to DPA attacks. HSPICE simulations for the test circuits using 0.18 µm TSMC CMOS process parameters indicate that SDL reduces power differences by an order of magnitude, compared to the existing circuit-level technique.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.1.234/_p

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@ARTICLE{e90-a_1_234,
author={Jong Suk LEE, Jae Woon LEE, Young Hwan KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Symmetric Discharge Logic against Differential Power Analysis},
year={2007},
volume={E90-A},
number={1},
pages={234-240},
abstract={Differential power analysis (DPA) is an effective technique that extracts secret keys from cryptographic systems through statistical analysis of the power traces obtained during encryption and decryption operations. This letter proposes symmetric discharge logic (SDL), a circuit-level countermeasure against DPA, which exhibits uniform power traces for every clock period by maintaining a set of discharge paths independent of input values. This feature minimizes differences in power traces and improves resistance to DPA attacks. HSPICE simulations for the test circuits using 0.18 µm TSMC CMOS process parameters indicate that SDL reduces power differences by an order of magnitude, compared to the existing circuit-level technique.},
keywords={},
doi={10.1093/ietfec/e90-a.1.234},
ISSN={1745-1337},
month={January},}

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TY - JOUR
TI - Symmetric Discharge Logic against Differential Power Analysis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 234
EP - 240
AU - Jong Suk LEE
AU - Jae Woon LEE
AU - Young Hwan KIM
PY - 2007
DO - 10.1093/ietfec/e90-a.1.234
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2007
AB - Differential power analysis (DPA) is an effective technique that extracts secret keys from cryptographic systems through statistical analysis of the power traces obtained during encryption and decryption operations. This letter proposes symmetric discharge logic (SDL), a circuit-level countermeasure against DPA, which exhibits uniform power traces for every clock period by maintaining a set of discharge paths independent of input values. This feature minimizes differences in power traces and improves resistance to DPA attacks. HSPICE simulations for the test circuits using 0.18 µm TSMC CMOS process parameters indicate that SDL reduces power differences by an order of magnitude, compared to the existing circuit-level technique.
ER -