This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.

The frequent and time-independent packet loss due to signal noise in the wireless network has been a major obstacle in providing a persistent end-to-end bandwidth in the integrated environment of wired and wireless networks. One approach to cope with this is to develop an efficient transport mechanism which appropriately adapts to the dynamics of the wireless part of the network so that the end-to-end throughput is maximised. The success of new transport mechanisms depends on the quality of information obtained, in particular, from the wireless network. This paper presents a novel mechanism to assess accurately the transmission quality of the wireless part of the integrated CDMA2000 1X networks using the NAK rate obtained from the underlying RLP protocol stack. The experiment results show that the proposed mechanism correctly measures the wireless transmission quality of the CDMA2000 1X network.