The search functionality is under construction.

Author Search Result

[Author] Jue WANG(2hit)

1-2hit
  • Multi-Party Electronic Contract Signing Protocol Based on Blockchain

    Tong ZHANG  Yujue WANG  Yong DING  Qianhong WU  Hai LIANG  Huiyong WANG  

     
    PAPER

      Pubricized:
    2021/12/07
      Vol:
    E105-D No:2
      Page(s):
    264-271

    With the development of Internet technology, the demand for signing electronic contracts has been greatly increased. The electronic contract generated by the participants in an online way enjoys the same legal effect as paper contract. The fairness is the key issue in jointly signing electronic contracts by the involved participants, so that all participants can either get the same copy of the contract or nothing. Most existing solutions only focus on the fairness of electronic contract generation between two participants, where the digital signature can effectively guarantee the fairness of the exchange of electronic contracts and becomes the conventional technology in designing the contract signing protocol. In this paper, an efficient blockchain-based multi-party electronic contract signing (MECS) protocol is presented, which not only offers the fairness of electronic contract generation for multiple participants, but also allows each participant to aggregate validate the signed copy of others. Security analysis shows that the proposed MECS protocol enjoys unforgeability, non-repudiation and fairness of electronic contracts, and performance analysis demonstrates the high efficiency of our construction.

  • An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression

    Yongpan LIU  Shuangchen LI  Jue WANG  Beihua YING  Huazhong YANG  

     
    PAPER-Integrated Electronics

      Vol:
    E94-C No:7
      Page(s):
    1220-1228

    This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.