IEICE TRANSACTIONS on Electronics
An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression
Summary :
This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.7 pp.1220-1228
- Publication Date
- 2011/07/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.1220
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Keyword
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Yongpan LIU, Shuangchen LI, Jue WANG, Beihua YING, Huazhong YANG, "An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 7, pp. 1220-1228, July 2011, doi: 10.1587/transele.E94.C.1220.
Abstract: This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1220/_p
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@ARTICLE{e94-c_7_1220,
author={Yongpan LIU, Shuangchen LI, Jue WANG, Beihua YING, Huazhong YANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression},
year={2011},
volume={E94-C},
number={7},
pages={1220-1228},
abstract={This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.},
keywords={},
doi={10.1587/transele.E94.C.1220},
ISSN={1745-1353},
month={July},}
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TY - JOUR
TI - An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression
T2 - IEICE TRANSACTIONS on Electronics
SP - 1220
EP - 1228
AU - Yongpan LIU
AU - Shuangchen LI
AU - Jue WANG
AU - Beihua YING
AU - Huazhong YANG
PY - 2011
DO - 10.1587/transele.E94.C.1220
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2011
AB - This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.
ER -
English
