The optimum tier architectures for ASICs are investigated by using a methodology for predicting packing efficiency of a logic block (the ratio of total cell area to the block area including space regions between cells). In the methodology based on Rent's rule, (1) the empirical parameters required for the prediction are derived from the results of our ASIC products. (2) The concept of logic distance, which is expressed in units of the number of cells rather than the absolute net length, is introduced. (3) Not only performance constraints but also reliability constraints are incorporated. These allow us to make a quantitative comparison of the packing efficiency between various cell and tier structures. It is found that, for mega-cell blocks, all minimum-pitch layer architecture with buffer insertion is expected to give more than 20% reduction in block areas compared to the minimum-pitch + bi-pitch architecture, while satisfying the performance and reliability constraints.

An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a Vcc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

A new bus architecture is proposed for reducing the operating power of future ULSI's. This architecture will relieve the constraint of the conventional supply voltage scaling, which makes it difficult to achieve both high speed and a low standby current if the supply voltage is scaled to less than 2 V. It employs new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration through the use of low-VT MOSFET's and an internal supply voltage corresponding to the reduced signal swing. Bus delay is almost halved with this driver when operated at 0.6-V swing and 2-V supply. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of new bus driver and bus receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining a high-speed data transmission and a low standby current. A test circuit is designed and fabricated using 0.3-µm processes. The operation of the proposed architecture was verified, and further improvements in the speed performance are expected by device optimization. The proposed architecture is promising for reducing the operating power of future ULSI's.