For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus is required to increase the system performance of multiprocessor environment. VME (versa module european package format) bus is appropriated to the standard bus but has the features that is the small of package and the low density of board. Beside, the density of board and semiconductor have grown to become a significant issues that affect the development time, project cost and field diagnostics. To fit this trend, in this paper, the author composed Revision C. 1 (IEEE Std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between VMEbus and several control modules. Also the designed VME system controller is implemented on FPGA that can be located even into Slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, the author confirmed that the most important about the operation of Bus timer that Bus error signal should occur within 56 µs, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.