A Study on the Design of VME System Controller

Kang Hyeon RHEE

A Study on the Design of VME System Controller

Kang Hyeon RHEE

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For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus is required to increase the system performance of multiprocessor environment. VME (versa module european package format) bus is appropriated to the standard bus but has the features that is the small of package and the low density of board. Beside, the density of board and semiconductor have grown to become a significant issues that affect the development time, project cost and field diagnostics. To fit this trend, in this paper, the author composed Revision C. 1 (IEEE Std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between VMEbus and several control modules. Also the designed VME system controller is implemented on FPGA that can be located even into Slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, the author confirmed that the most important about the operation of Bus timer that Bus error signal should occur within 56 µs, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.6 pp.1083-1090

Publication Date: 2000/06/25

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Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))

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Kang Hyeon RHEE, "A Study on the Design of VME System Controller" in IEICE TRANSACTIONS on Fundamentals, vol. E83-A, no. 6, pp. 1083-1090, June 2000, doi: .
Abstract: For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus is required to increase the system performance of multiprocessor environment. VME (versa module european package format) bus is appropriated to the standard bus but has the features that is the small of package and the low density of board. Beside, the density of board and semiconductor have grown to become a significant issues that affect the development time, project cost and field diagnostics. To fit this trend, in this paper, the author composed Revision C. 1 (IEEE Std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between VMEbus and several control modules. Also the designed VME system controller is implemented on FPGA that can be located even into Slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, the author confirmed that the most important about the operation of Bus timer that Bus error signal should occur within 56 µs, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1083/_p

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@ARTICLE{e83-a_6_1083,
author={Kang Hyeon RHEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Study on the Design of VME System Controller},
year={2000},
volume={E83-A},
number={6},
pages={1083-1090},
abstract={For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus is required to increase the system performance of multiprocessor environment. VME (versa module european package format) bus is appropriated to the standard bus but has the features that is the small of package and the low density of board. Beside, the density of board and semiconductor have grown to become a significant issues that affect the development time, project cost and field diagnostics. To fit this trend, in this paper, the author composed Revision C. 1 (IEEE Std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between VMEbus and several control modules. Also the designed VME system controller is implemented on FPGA that can be located even into Slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, the author confirmed that the most important about the operation of Bus timer that Bus error signal should occur within 56 µs, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A Study on the Design of VME System Controller
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1083
EP - 1090
AU - Kang Hyeon RHEE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus is required to increase the system performance of multiprocessor environment. VME (versa module european package format) bus is appropriated to the standard bus but has the features that is the small of package and the low density of board. Beside, the density of board and semiconductor have grown to become a significant issues that affect the development time, project cost and field diagnostics. To fit this trend, in this paper, the author composed Revision C. 1 (IEEE Std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between VMEbus and several control modules. Also the designed VME system controller is implemented on FPGA that can be located even into Slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, the author confirmed that the most important about the operation of Bus timer that Bus error signal should occur within 56 µs, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.
ER -