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[Author] Katsufusa SHOHNO(1hit)

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  • A Mos Inverter Circuit with Poly-Si Self-Aligned Gate for Educational Purposes to Engineering Students

    Katsufusa SHOHNO  

     
    PAPER-Integrated Circuits

      Vol:
    E62-E No:9
      Page(s):
    590-594

    A step-by-step approach to the fabrication and analysis of a p-MOS inverter circuit using poly-Si self-aligned gates outlines a possible experimental course in MOS technology, suitable to run concurrently with the lecture course on semiconductor integrated circuits. The fabrication process which uses oxidation, diffusion and evaporation techniques and two photolithographic process can usually be performed in four afternoon experimental sessions. The capital outlay and actual running cost of the course are modest enough to open almost any engineering department to MOS technology. The basic concepts of the p-n junction, MOS diode, MOS transistor and inverter operation are fully illustrated in the inverter circuit presented.