A pitch of a grating drawn by an electron beam was controlled precisely within 10 by attaching an attenuator to a conventional electron-beam-exposure system. This technique may be applied for fabrication of a periodic structure for integrated optics.

We propose a decoding algorithm for the t-EC/AUED code proposed by Böinck and Tiborg. The proposed algorithm also reveals some remarkable properties of the code.

This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.

In this paper, we consider the behavior of an autoregressive (AR) detector for partial-response (PR) signaling against offtrack interference (OTI) environment in perpendicular magnetic recording. Based on the behavior, we derive the optimum branch metric to construct the detector by the Viterbi algorithm. We propose an optimum AR detector for OTI that considers an optimum branch metric calculation and an estimation of noise power due to OTI in order to calculate an accurate branch metric. To evaluate the reliability of soft-output likelihood values calculated by our proposed AR detector, we demonstrate a bit error rate performance (BER) of low-density parity-check (LDPC) codes under OTI existing channel by computer simulation. Our simulation results show the proposed AR detector can achieve a better LDPC-coded BER performance than the conventional AR detector. We also show the BER performance of our proposal can keep within 0.5 dB of the case that perfect channel state information regarding OTI is used in the detector. In addition, we show that the partial-response maximum-likelihood (PRML) detector is robust against OTI even if OTI is not handled by the detector.