1-3hit |
Koji ASAMI Takahide SUZUKI Hiroyuki MIYAJIMA Tetsuya TAURA Haruo KOBAYASHI
One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique for automatic test equipment applications. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.
It is essential, as bandwidths of wireless communications get wider, to evaluate the imbalances among quadrature mixer ports, in terms of carrier phase offset, IQ gain imbalance, and IQ skew. Because it is time consuming to separate skew, gain imbalance and carrier phase offset evaluation during test is often performed using a composite value, without separation of the imbalance factors. This paper describes an algorithm for enabling separation among quadrature mixer gain imbalance, carrier phase offset, and skew. Since the test time is reduced by the proposed method, it can be applied during high volume production testing.
One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.