An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0. 8 µ m n-well CMOS double metal/single poly process occupies the chip area of 2. 2 mm 1. 6 mm. The experimental result shows the power dissipation of 33. 6 mW with a power supply of 5 V.