An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers

Kyung-Myun KIM; Kwang Sub YOON

An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers

Kyung-Myun KIM, Kwang Sub YOON

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An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0. 8 µ m n-well CMOS double metal/single poly process occupies the chip area of 2. 2 mm 1. 6 mm. The experimental result shows the power dissipation of 33. 6 mW with a power supply of 5 V.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.2 pp.252-255

Publication Date: 1998/02/25

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Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)

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Kyung-Myun KIM, Kwang Sub YOON, "An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 2, pp. 252-255, February 1998, doi: .
Abstract: An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0. 8 µ m n-well CMOS double metal/single poly process occupies the chip area of 2. 2 mm 1. 6 mm. The experimental result shows the power dissipation of 33. 6 mW with a power supply of 5 V.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_2_252/_p

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@ARTICLE{e81-a_2_252,
author={Kyung-Myun KIM, Kwang Sub YOON, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers},
year={1998},
volume={E81-A},
number={2},
pages={252-255},
abstract={An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0. 8 µ m n-well CMOS double metal/single poly process occupies the chip area of 2. 2 mm 1. 6 mm. The experimental result shows the power dissipation of 33. 6 mW with a power supply of 5 V.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 252
EP - 255
AU - Kyung-Myun KIM
AU - Kwang Sub YOON
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1998
AB - An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0. 8 µ m n-well CMOS double metal/single poly process occupies the chip area of 2. 2 mm 1. 6 mm. The experimental result shows the power dissipation of 33. 6 mW with a power supply of 5 V.
ER -