This paper describes our recent developments of ASICs for automotive multiplexing and data communications to implement in-vehicle networks. With the advancement of automotive electronics, there are ever growing needs for in-vehicle networks. One need is associated with solving the problem of an increasing number of electrical signal wires that inevitably accompany the increasing applications of automotive electronics. Another kind of need is concerned with sharing vehicle control data among several electronic control units such as engine, brake, suspension, and steering electronic control units to achieve an integrated vehicle control system for the purpose of obtaining higher performances in vehicle dynamics. In order to reduce the number of signal wires and share the control data, in-vehicle networks based on multiplexing and data communications are required. In this paper, two original communication protocols are presented to respectively cover low- and highi-speed multiplexing and data communications that are two most needed communication speed areas in our present and future automobiles. ASICs for the presented communication protoclos were designed and fabricated, using 2 µm COMS process. They have the chip size of 3.2 mm2.7 mm with 5,000 transistors and 6.9 mm4.9 mm with 18,000 transistors respectively for low- and high-speed multiplexing and data communications. An elaborate bus driver/receiver ASIC required for high-speed multiplexing and data communications was also designed and fabricated, using 35 V DC bipolar process. As one of its distinctive features, it can greatly suppress radio frequency noise radiated from a communication bus. It has the chip size of 4.8 mm3.8 mm that contains 570 device elements. The features of the protocols are given in detail with the descriptions of the developed ASICs.

Neural networks are widely used in various fields due to their superior learning abilities. This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL), and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a global winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the WTA in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning.