Scalable Hardware Winner-Take-All Neural Network with DPLL

Masaki AZUMA; Hiroomi HIKAWA

doi:10.1587/transinf.2014EDP7371

IEICE TRANSACTIONS on Information

Scalable Hardware Winner-Take-All Neural Network with DPLL

Masaki AZUMA, Hiroomi HIKAWA

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Neural networks are widely used in various fields due to their superior learning abilities. This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL), and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a global winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the WTA in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning.

Publication: IEICE TRANSACTIONS on Information Vol.E98-D No.10 pp.1838-1846

Publication Date: 2015/10/01

Publicized: 2015/07/21

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2014EDP7371

Type of Manuscript: PAPER

Category: Biocybernetics, Neurocomputing

Authors

Masaki AZUMA
Aisin Seiki Co., Ltd.
Hiroomi HIKAWA
Kansai University

Keyword

neural network, winner-take-all, supervised learning, digital phase-locked loop, hardware architecture

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Masaki AZUMA, Hiroomi HIKAWA, "Scalable Hardware Winner-Take-All Neural Network with DPLL" in IEICE TRANSACTIONS on Information, vol. E98-D, no. 10, pp. 1838-1846, October 2015, doi: 10.1587/transinf.2014EDP7371.
Abstract: Neural networks are widely used in various fields due to their superior learning abilities. This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL), and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a global winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the WTA in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014EDP7371/_p

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@ARTICLE{e98-d_10_1838,
author={Masaki AZUMA, Hiroomi HIKAWA, },
journal={IEICE TRANSACTIONS on Information},
title={Scalable Hardware Winner-Take-All Neural Network with DPLL},
year={2015},
volume={E98-D},
number={10},
pages={1838-1846},
abstract={Neural networks are widely used in various fields due to their superior learning abilities. This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL), and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a global winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the WTA in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning.},
keywords={},
doi={10.1587/transinf.2014EDP7371},
ISSN={1745-1361},
month={October},}

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TY - JOUR
TI - Scalable Hardware Winner-Take-All Neural Network with DPLL
T2 - IEICE TRANSACTIONS on Information
SP - 1838
EP - 1846
AU - Masaki AZUMA
AU - Hiroomi HIKAWA
PY - 2015
DO - 10.1587/transinf.2014EDP7371
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E98-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2015
AB - Neural networks are widely used in various fields due to their superior learning abilities. This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL), and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a global winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the WTA in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning.
ER -

IEICE TRANSACTIONS on Information