A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (Dll) for deskew, and a frequency-locked loop(FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector newly developed which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4µm CMOS technology is used to fabricate the chip.