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[Author] Masashi TODA(4hit)

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  • Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade

    Junichi AKITA  Hiroaki TAKAGI  Keisuke DOUMAE  Akio KITAGAWA  Masashi TODA  Takeshi NAGASAKI  Toshio KAWASHIMA  

     
    PAPER-Image Sensor/Vision Chip

      Vol:
    E90-C No:10
      Page(s):
    1869-1875

    Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.

  • Extraction Method of Scallop Area from Sand Seabed Images

    Koichiro ENOMOTO  Masashi TODA  Yasuhiro KUWAHARA  

     
    PAPER-Pattern Recognition

      Vol:
    E97-D No:1
      Page(s):
    130-138

    The results of fishery investigations are used to estimate the catch size, times fish are caught, and future stock in the fish culture industry. In Tokoro, Japan, scallop farms are located on gravel and sand seabed. Seabed images are necessary to visually estimate the number of scallops of a particular farm. However, there is no automatic technology for measuring resources quantities and so the current investigation technique is the manual measurement by experts. We propose a method to extract scallop areas from images of sand seabed. In the sand field, we can see only the shelly rim because the scallop is covered with sand and opens and closes its shell while it is alive and breathing. We propose a method to extract the shelly rim areas under varying illumination, extract the scallop areas using the shelly rims based on professional knowledge of the sand field, explain the results, and evaluate the method's effectiveness.

  • Extraction Method of Scallop Area in Gravel Seabed Images for Fishery Investigation

    Koichiro ENOMOTO  Masashi TODA  Yasuhiro KUWAHARA  

     
    PAPER

      Vol:
    E93-D No:7
      Page(s):
    1754-1760

    The quantity and state of fishery resources must be known so that they can be sustained. The fish culture industry is also planning to investigate resources. The results of investigations are used to estimate the catch size, times fish are caught, and future stocks. We have developed a method for extracting scallop areas from gravel seabed images to assess fish resources and also developed an automatic system that measures their quantities, sizes, and states. Japanese scallop farms for fisheries are found on gravel and sand seabeds. The seabed images are used for fishery investigations, which are absolutely necessary to visually estimate, and help us avoid using the acoustic survey. However, there is no automatic technology to measure the quantities, sizes, and states of resources, and so the current investigation technique is the manual measurement by experts. There are varied problems in automating technique. The photography environments have a high degree of noise, including large differences in lighting. Gravel, sand, clay, and debris are also included in the images. In the gravel field, we can see scallop features, such as colors, striped patterns, and fan-like shapes. This paper describes the features of our image extracting method, presents the results, and evaluates its effectiveness.

  • Vision Chip Architecture for Detecting Line of Sight Including Saccade

    Junichi AKITA  Hiroaki TAKAGI  Takeshi NAGASAKI  Masashi TODA  Toshio KAWASHIMA  Akio KITAGAWA  

     
    PAPER

      Vol:
    E89-C No:11
      Page(s):
    1605-1611

    Rapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture.