IEICE TRANSACTIONS on Electronics
Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade
Summary :
Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.10 pp.1869-1875
- Publication Date
- 2007/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.10.1869
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
- Category
- Image Sensor/Vision Chip
Authors
Keyword
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Junichi AKITA, Hiroaki TAKAGI, Keisuke DOUMAE, Akio KITAGAWA, Masashi TODA, Takeshi NAGASAKI, Toshio KAWASHIMA, "Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 10, pp. 1869-1875, October 2007, doi: 10.1093/ietele/e90-c.10.1869.
Abstract: Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.10.1869/_p
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@ARTICLE{e90-c_10_1869,
author={Junichi AKITA, Hiroaki TAKAGI, Keisuke DOUMAE, Akio KITAGAWA, Masashi TODA, Takeshi NAGASAKI, Toshio KAWASHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade},
year={2007},
volume={E90-C},
number={10},
pages={1869-1875},
abstract={Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.},
keywords={},
doi={10.1093/ietele/e90-c.10.1869},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade
T2 - IEICE TRANSACTIONS on Electronics
SP - 1869
EP - 1875
AU - Junichi AKITA
AU - Hiroaki TAKAGI
AU - Keisuke DOUMAE
AU - Akio KITAGAWA
AU - Masashi TODA
AU - Takeshi NAGASAKI
AU - Toshio KAWASHIMA
PY - 2007
DO - 10.1093/ietele/e90-c.10.1869
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2007
AB - Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.
ER -
English
