A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.

This paper deals with CE-SS (Constant-Envelope Spread Spectrum) signals, focusing on a novel generation technique based upon using digital processing blocks to drive a frequency modulator with a random sequence. The system described herein allows for flexibility in achieving a variety of user defined goal spectra. The foundation upon which this work is built was laid by Callegari et al. who introduced a novel synthesis procedure for 'non-stationary' modulations. This novel synthesis technique uses an iterative algorithm to arrive at an output spectrum which is a good approximation to a user-defined goal spectrum. The architecture which this paper details uses programmable logic to tune the system parameters in striving towards user defined goal spectra. The architecture can generate CE-SS waveforms whose spectra match those which the aforementioned algorithm deems achievable.

In order to demodulate a Differential Chaos Shift Keying (DCSK) signal, the energy carried by the received chaotic signal must be determined. Since a chaotic signal is not periodic, the energy per bit carried by the chaotic signal can only be estimated, even in the noise-free case. This estimation has a non-zero variance that limits the attainable data rate. In this paper the DCSK technique is combined with frequency modulation in order to overcome the estimation problem and to improve the data rate of DCSK modulation.

The fact that there exists a core sinusoidal oscillator at the heart of Saito's double-screw hysteresis chaotic oscillator is demonstrated. By applying Bruton's transformation to the active linear part of the circuit, which is shown to be a classical LC-R negative resistor sinusoidal oscillator, an inductorless realization based on a frequency-dependent negative resistor (FDNR) is obtained. The LC-R sinusoidal oscillator is replaced by an FDNR-R oscillator. Furthermore, we show that chaotic behaviour can be preserved when a simple minimum component 2R-2C sinusoidal oscillator is used. Two different realizations of the non-monotone current-controlled hysteresis resistor, one of which is completely passive, are investigated. Experimental results of selected circuits, PSpice and numerical simulations are included.