IEICE TRANSACTIONS on Fundamentals
Modeling and Simulation of ΔΣ Fractional-N PLL Frequency Synthesizer in Verilog-AMS
Summary :
A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.10 pp.2141-2147
- Publication Date
- 2007/10/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.10.2141
- Type of Manuscript
- Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
- Category
- Nonlinear Circuits
Authors
Keyword
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Zhipeng YE, Wenbin CHEN, Michael Peter KENNEDY, "Modeling and Simulation of ΔΣ Fractional-N PLL Frequency Synthesizer in Verilog-AMS" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 10, pp. 2141-2147, October 2007, doi: 10.1093/ietfec/e90-a.10.2141.
Abstract: A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.10.2141/_p
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@ARTICLE{e90-a_10_2141,
author={Zhipeng YE, Wenbin CHEN, Michael Peter KENNEDY, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modeling and Simulation of ΔΣ Fractional-N PLL Frequency Synthesizer in Verilog-AMS},
year={2007},
volume={E90-A},
number={10},
pages={2141-2147},
abstract={A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.},
keywords={},
doi={10.1093/ietfec/e90-a.10.2141},
ISSN={1745-1337},
month={October},}
Copy
TY - JOUR
TI - Modeling and Simulation of ΔΣ Fractional-N PLL Frequency Synthesizer in Verilog-AMS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2141
EP - 2147
AU - Zhipeng YE
AU - Wenbin CHEN
AU - Michael Peter KENNEDY
PY - 2007
DO - 10.1093/ietfec/e90-a.10.2141
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2007
AB - A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.
ER -
English
