This paper presents an alternative traffic model for an ATM multiplexer providing video, voice, image, and data services. The traffic model classifies the input traffic into two types: real-time and non-real-time. The input process for realtime traffic is periodic and correlated, while that for non-realtime traffic is batch Poisson and independent. This multiplexer is assumed to be a priority queueing system with synchronous servers operating on time-frame basis and with separate finite buffers for each type of traffic. State probabilities and performance measures are successfully obtained using a Markov analysis technique and an application of the residue theorem in complex variable. The results can be applied in the design of an ATM multiplexer.

The paper studies a high-ranking node in a broadband integrated services digital network(B-ISDN). The input traffic is classified into two types: real-time and non-real-time. For each type of input traffic, we assume that the message arrival process is a batch Poisson process and that the message size is arbitrarily distributed so as to describe services from narrowband to wideband. We model the high-ranking node by a queueing system with multiple synchronous servers and two separate finite buffers, one for each type of traffic. We derive performance measures exactly by using a two-dimensional imbedded discrete-time Markov chain analysis, within which the transition probabilities are obtained via an application of the residue theorem in complex variables. The performance measures include the blocking probability, delay, and throughput.

In an Multi-Protocol Label Switching (MPLS) network domain, Asynchronous Transfer Mode--Label Switch Routers (ATM-LSRs) are considered the best candidate for providing the highest forwarding capability. ATM-LSRs implement a VC-merging scheme that allows many IP routes to be mapped into the same VPI/VCI label, hence supporting scalability. The VC-merging requires reassembly buffers to reconstruct an original packet from its segmented but interleaved AAL-5 cells. In this paper, we analyze the performance of an ATM-LSR with partial VC-merging capability and investigate the impact of VC-merging on the requirement of the reassembly and output buffer. The numerical computation complexity of the mathematical analysis can be reduced from O(M4) to O(M2), where M is the total number of ON-OFF sources. We also propose a closed-form equation, which approximates the distribution of the output buffer with satisfactory accuracy. Numerical results show that when incoming cells are severely interleaved, the VC-merging needs the reassembly buffer size to be of the same order as the output buffer size, which cannot be ignored.