In this paper we present the successful application of Prime Factor Algorithm FFT (Fast Fourier Transform) and pruning techniques to achieve low complexity UTRA-TDD detection. This approach has been applied to the Minimum Mean Square Error-Block Linear Equalizer (MMSE-BLE) receiver and to an MMSE equalizer specially designed for the downlink after their proper reformulation in the frequency domain. A complexity reduction of nearly 50% with respect to the classical 2n length FFT solutions has been demonstrated, without any performance loss. A more parallelizable VLSI architecture can be derived thanks to the modularity of the introduced FFT algorithms. Performances comparison has been carried out to confirm the validity of the proposed methods.